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Op Amp Input Stages

It is extremely important to understand input and output structures of op amps in order to properly design the required interfaces. For ease of discussion, the two can be examined separately, as there is no particular reason to relate them at this point.
Bipolar Input Stages
The very common and basic bipolar input stage of Figure 1-21 below consists of a "long-tailed pair" built with bipolar transistors. It has a number of advantages: it is simple, has very low offset, the bias currents in the inverting and non-inverting inputs are well-matched and do not vary greatly with temperature. In addition, minimizing the initial offset voltage of a bipolar op amp by laser trimming also minimizes its drift over temperature. This architecture was used in the very earliest monolithic op amps such as the μA709. It is also used with modern high speed types, like the AD829 and AD8021. Although NPN bipolars are shown, the concept also applies with the use of PNP bipolars.
A bipolar transistor input stage
Figure 1-21: A bipolar transistor input stage
The AD829, introduced in 1990, is shown in Figure 1-22 (opposite). This op amp uses a bipolar differential input stage, Q1-Q2, which drives a "folded cascode" gain stage which consists of a fast pair of PNP transistors, Q3-Q4 (Reference 1: "Video Op Amp," Analog Dialogue, Vol. 24, No. 3, pp. 19). These PNPs drive a current mirror that provides the differential-to-single-ended conversion. The output stage is a two-stage complementary emitter follower.
The AD829 is a wideband video amplifier with a 750MHz uncompensated gain-bandwidth product, and it operates on ±5V to ±15V supplies. For added flexibility, the AD829 provides access to the internal compensation node (CCOMP). This allows the user to customize frequency response characteristics for a particular application where the closed-loop gain is less than 20. The RC network connected between the output and the high impedance node helps maintain stability, when driving capacitive loads.
Input bias current is 7μA maximum at +25°C, input voltage noise is 1.7nV/√Hz, and input current noise is 1.5pA/√Hz. Laser wafer trimming reduces the input offset voltage to 0.5mV maximum for the "A" grade. Typical input offset voltage drift is 0.3μV/°C.
In an op amp input circuit such as Fig. 1-22, the input bias current is the base current of the transistors comprising the long-tailed pair, Q1-Q2. It can be quite high, especially in high speed amplifiers, because the collector currents are high. It is typically ~3μA, for the AD829. In amplifiers where the bias current is uncompensated (as true in this case), the bias current will be equal to ½ the Q1-Q2 emitter current, divided by the HFE.
The bias current of a simple bipolar input stage can be reduced by a couple of measures. One is by means of bias current compensation, to be described further below.
AD829 op amp simplified schematic
Figure 1-22: AD829 op amp simplified schematic
Another method of reducing bias current is by the use of super-beta transistors for Q1-Q2. Super-beta transistors are specially processed devices with a very narrow base region. They typically have a current gain of thousands or tens of thousands (rather than the more usual hundreds). Op amps with super-beta input stages have much lower bias currents, but they also have more limited frequency response.
Since the breakdown voltages of super-beta devices are quite low, they also require additional circuitry to protect the input stage from damage caused by over-voltage (for example, they wouldn't operate in the circuit of Fig. 1-22).
Some examples of super-beta input bipolar op amps are the AD704/705/706 series, and the OP97/297/497 series (single, dual, quad). These devices have typical 25°C bias currents of 100pA or less.
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