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The Planar Process

In general parallel with the Noyce’s early IC developments, Jean Hoerni (also of Fairchild Semiconductor) had been working on means to protect and stabilize silicon diode and transistor characteristics. Until that time, the junctions of all mesa process devices were essentially left exposed. This was a serious limitation of the mesa process.
The mesa process is so-named because the areas surrounding the central base-emitter regions are etched away, thus leaving this area exposed on a plateau, or mesa. In practice, this factor makes a semiconductor so constructed susceptible to contaminants, and as a result, inherently less stable. This was the fatal flaw that Hoerni’s invention addressed.
Hoerni’s solution to the problem was to re-arrange the transistor geometry into a flat, or planar surface, thus giving the new process its name (References 7 and 8: Jean A. Hoerni, "Method of Manufacturing Semiconductor Devices," US Patent 3,025,589, filed May 1, 1959, issued March 20, 1962 (the planar process— a manufacturing means of protecting and stabilizing semiconductors) and Jean Hoerni, "Planar Silicon Diodes and Transistors," IRE Transactions on Electron Devices, Vol. 8, March 1961, p. 168 (technical discussion of planar processed devices)). However, the important distinction in terms of device protection is that within the planar process the otherwise exposed regions are left covered with silicon dioxide. This feature reduced the device sensitivity to contaminants; making a much better, more stable transistor or IC.
With the arrangement of the device terminals on a planar surface, Hoerni’s invention was also directly amenable to the flat metal conducting traces that were intrinsic to Noyce’s IC invention. Furthermore, the planar process required no additional process steps in its implementation, so it made the higher performance economical as well. As time has now shown, the development of the planar process was another key semiconductor invention. It is now widely used in production of transistors and ICs.
At a time in the early 1960s shortly after the invention of the planar process, the three key developments had been made. They were the (silicon) transistor itself, the IC, and the planar process. The stage was now set for important solid-state developments in op amps. This was to take place in three stages. First, there would be discrete transistor and modular op amp versions, second there would be hybrid op amps, which could be produced in a couple of ways. One hybrid method utilized discrete transistors in chip form(s), interconnected to form an op amp; another was a specially matched transistor pair combined with an IC op amp for improved performance, and thirdly, the op amp finally became a complete, integral, dedicated IC— the IC op amp. This latter developmental stage is covered more fully within the next section of this chapter.
Of course, within these developmental stages there were considerable improvements made to device performance. And, as with the vacuum tube/solid-state periods, each stage overlapped the previous and/or the next one to a great extent.
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