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Bias Current Compensated Super-Beta Bipolar Input Stage

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As mentioned above, the OP97/297/497-series are high performance super-beta op amps, which also use input bias current compensation. As a result, their input bias currents are ±150pA max at 25°C. Note that in this case the "±" prefix to the bias current magnitude indicates that the amplifier uses internal bias current compensation.
A simplified schematic of an OP97 (or ¼ of the OP497) is shown in Figure 1-25 below. Note that the Q1-Q2 super-beta pair is protected against large destructive differential input voltages, by the use of both back-to-back diodes, and series current-limiting resistors. Note also that Q1-Q2 super-beta pair is also protected against excessive collector voltage, by an elaborate bias and bootstrapping network.
The OP97, OP297 and OP497 op amp series uses super-beta input stage transistors and bias current compensation
Figure 1-25: The OP97, OP297 and OP497 op amp series uses super-beta input stage transistors and bias current compensation
As a result of these clamping and protection circuits, the input common-mode voltage of this op amp series can safely vary over the full range of the supply voltages used.
FET Input Stages
Field-Effect Transistors (FETs) have much higher input impedance than do bipolar junction transistors (BJTs) and would therefore seem to be ideal devices for op amp input stages. However, they cannot be manufactured on all bipolar IC processes, and when a process does allow their manufacture, they often have their own problems.
FETs have high input impedance, low bias current, and good high frequency performance (in an op amp, the lower gm of the FET devices allows higher tail currents, thereby increasing the maximum slew rate). FETs also have much lower current noise.
On the other hand, the input offset voltage of FET long-tailed pairs, however, is not as good as the offset of corresponding BJTs, and trimming for minimum offset does not simultaneously minimize drift. A separate trim is needed for drift, and as a result, offset and drift in a JFET op amp, while good, aren't as good as the best BJT ones. A simplified trim procedure for an FET input op amp stage is shown in Figure 1-26 below.
It is possible to make JFET op amps with very low voltage noise, but the devices involved are very large and have quite high input capacitance, which varies with input voltage, and so a trade-off is involved between voltage noise and input capacitance.
The bias current of an FET op amp is the leakage current of the gate diffusion (or the leakage of the gate protection diode, which has similar characteristics for a MOSFET). Such leakage currents double with every 10°C increase in chip temperature so that a FET op amp bias current is one thousand times greater at 125°C than at 25°C. Obviously this can be important when choosing between a bipolar or FET input op amp, especially in high temperature applications where bipolar op amp input bias current actually decreases.
Junction field effect transistor (JFET) input op amp stage showing offset and drift trims
Figure 1-26: Junction field effect transistor (JFET) input op amp stage showing offset and drift trims
Thus far, we have spoken generally of all kinds of FETs, that is junction (JFETs) and MOS (MOSFETs). In practice, combined bipolar/JFET technology op amps (i.e., BiFET) achieve better performance than op amps using purely MOSFET or CMOS technology. While ADI and others make high performance op amps with MOS or CMOS input stages, in general these op amps have worse offset and drift, voltage noise, high-frequency performance than the bipolar counterparts. The power consumption is usually somewhat lower than that of bipolar op amps with comparable, or even better, performance.
JFET devices require more headroom than do BJTs, since their pinchoff voltage is typically greater than a BJTs base-emitter voltage. Consequently, they are more difficult to operate at very low power supply voltages (1-2V). In this respect, CMOS has the advantage of requiring less headroom than JFETs.
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