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Rail-Rail Input Stages

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Today, there is common demand for op amps with input CM voltage that includes both supply rails, i.e., rail-to-rail CM operation. While such a feature is undoubtedly useful in some applications, engineers should recognize that there are still relatively few applications where it is absolutely essential. These applications should be distinguished from the many more applications where a CM range close to the supplies, or one that includes one supply is necessary, but true input rail-to-rail operation is not.
In many single-supply applications, it is required that the input CM voltage range extend to one of the supply rails (usually ground). High-side or low-side current-sensing applications are examples of this. Many amplifiers can handle 0V CM inputs, and they are easily designed using PNP differential pairs (or N-channel JFET pairs) as shown in Figure 1-27 below. The input CM range of such an op amp generally extends from about 200mV below the negative rail (-VS or ground), to about 1-2V of the positive rail, +VS.
PNP or N-channel JFET stages allow CM inputs to the negative rail
Figure 1-27: PNP or N-channel JFET stages allow CM inputs to the negative rail
An input stage could also be designed with NPN transistors (or P-channel JFETs), in which case the input CM range would include the positive rail, and go to within about 1-2V of the negative rail. This requirement typically occurs in applications such as high-side current sensing. The OP282/OP482 input stage uses a P-channel JFET input pair whose input CM range includes the positive rail, making it suitable for high-side sensing.
The AD823 is a dual 16MHz (G = +1) op amp with an N-channel JFET input stage (as in Fig. 1-27 right). A simplified schematic of the AD823 is shown in Figure 1-28 (opposite). This device can operate on single-supply voltages from +3 to +36V. This range also allows operation on traditional ±5V, or ±15V dual supplies if desired. Similar devices in a related (but lower power) family include the AD820, the AD822, and the AD824.
The AD823 JFET input stage allows the input common-mode voltage to range from 200mV below the negative supply to within about 1.5V of the positive supply. Input offset voltage is 0.8mV maximum at +25°C, input bias current is 25pA maximum at +25°C, offset voltage drift is 2μV/°C, and input voltage noise is 16nV/√Hz. Current noise is only 1fA/√Hz. The AD823 is laser wafer trimmed for both offset voltage and offset voltage drift as described above.
AD823 JFET input op amp simplified schematic
Figure 1-28: AD823 JFET input op amp simplified schematic
A simplified diagram of a true rail-to-rail input stage is shown in Figure 1-29 below. Note that this requires use of two long-tailed pairs, one of PNP bipolar transistors Q1-Q2, the other of NPN transistors Q3-Q4. Similar input stages can also be made with CMOS pairs.
A true rail-to-rail bipolar transistor input stage
Figure 1-29: A true rail-to-rail bipolar transistor input stage
It should be noted that these two pairs will exhibit different offsets and bias currents, so when the applied CM voltage changes, the amplifier input offset voltage and input bias current does also. In fact, when both current sources remain active throughout most of the entire input common-mode range, amplifier input offset voltage is the average offset voltage of the two pairs. In those designs where the current sources are alternatively switched off at some point along the input common-mode voltage, amplifier input offset voltage is dominated by the PNP pair offset voltage for signals near the negative supply, and by the NPN pair offset voltage for signals near the positive supply. As noted, a true rail-to-rail input stage can also be constructed from CMOS transistors, for example as in the case of the CMOS AD8531/8532/8534 op amp family.
Amplifier input bias current, a function of transistor current gain, is also a function of the applied input common-mode voltage. The result is relatively poor common-mode rejection (CMR), and a changing common-mode input impedance over the CM input voltage range, compared to familiar dual-supply devices. These specifications should be considered carefully when choosing a rail-to-rail input op amp, especially for a non-inverting configuration. Input offset voltage, input bias current, and even CMR may be quite good over part of the common-mode range, but much worse in the region where operation shifts between the NPN and PNP devices, and vice versa.
True rail-to-rail amplifier input stage designs must transition from one differential pair to the other differential pair, somewhere along the input CM voltage range. Some devices like the OP191/291/491 family and the OP279 have a common-mode crossover threshold at approximately 1V below the positive supply (where signals do not often occur). The PNP differential input stage is active from about 200mV below the negative supply to within about 1V of the positive supply. Over this common-mode range, amplifier input offset voltage, input bias current, CMR, input noise voltage/current are primarily determined by the characteristics of the PNP differential pair. At the crossover threshold, however, amplifier input offset voltage becomes the average offset voltage of the NPN/PNP pairs and can change rapidly.
Also, as noted previously, amplifier bias currents are dominated by the PNP differential pair over most of the input common-mode range, and change polarity and magnitude at the crossover threshold when the NPN differential pair becomes active.
Op amps like the OP184/284/484 family, shown in Figure 1-30 opposite, utilize a rail-to-rail input stage design where both NPN and PNP transistor pairs are active throughout most of the entire input CM voltage range. With this approach to biasing, there is no CM crossover threshold. Amplifier input offset voltage is the average offset voltage of the NPN and the PNP stages, and offset voltage exhibits a smooth transition throughout the entire input CM range, due to careful laser trimming of input stage resistors.
In the same manner, through careful input stage current balancing and input transistor design, the OP184 family input bias currents also exhibit a smooth transition throughout the entire CM input voltage range. The exception occurs at the very extremes of the input range, where amplifier offset voltages and bias currents increase sharply, due to the slight forward-biasing of parasitic p-n junctions. This occurs for input voltages within approximately 1V of either supply rail.
When both differential pairs are active throughout most of the entire input common-mode range, amplifier transient response is faster through the middle of the common-mode range by as much as a factor of 2 for bipolar input stages and by a factor of √2 for JFET input stages. This is due to the higher transconductance of two operating input stages.
Input stage gm determines the slew rate and the unity-gain crossover frequency of the amplifier, hence response time degrades slightly at the extremes of the input common-mode range when either the PNP stage (signals approaching the positive supply rail) or the NPN stage (signals approaching the negative supply rail) are forced into cutoff. The thresholds at which the transconductance changes occur are approximately within 1V of either supply rail, and the behavior is similar to that of the input bias currents.
OP284 op amp simplified schematic shows true rail-to-rail input stage
Figure 1-30: OP284 op amp simplified schematic shows true rail-to-rail input stage
In light of the many quirks of true rail-to-rail op amp input stages, applications which do require true rail-to-rail inputs should be carefully evaluated, and an amplifier chosen to ensure that its input offset voltage, input bias current, common-mode rejection, and noise (voltage and current) are suitable.
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