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VFB Op Amps Designed on Complementary Bipolar Processes

previous Voltage Feedback (VFB) Op Amps
With the advent of complementary bipolar (CB) processes having high quality PNP transistors as well as NPNs, VFB op amp configurations such as the one shown in the simplified diagram in Figure 1-100 below became popular.
VFB op amp using two gain stages
Figure 1-100: VFB op amp using two gain stages
Notice that the input differential pair (Q1, Q2) is loaded by a current mirror (Q3 and D1). We show D1 as a diode for simplicity, but it is actually a diode-connected PNP transistor (matched to Q3) with the base and collector connected to each other. This simplification will be used in many of the circuit diagrams to follow in this section. The common emitter transistor, Q4, provides a second voltage gain stage.
Model for two stage VFB op amp
Figure 1-101: Model for two stage VFB op amp
Since the PNP transistors are fabricated on a complementary bipolar process, they are high quality and matched to the NPNs, and therefore suitable for voltage gain. The dominant pole of the Fig. 1-100 amplifier is set by CP, and the combination of the gain stage, Q4 and local feedback capacitor CP is often referred to as a Miller Integrator. The unity-gain output buffer is usually a complementary emitter follower.
A model for this two-stage VFB op amp is shown in Figure 1-101 above. Notice that the unity gain-bandwidth frequency, fu, is still determined by the input stage gm and the dominant pole capacitance, CP. The second gain stage increases the DC open-loop gain, but maximum slew rate is still limited by the input stage tail current as: SR = IT/CP.
A two-stage amplifier topology such as this is widely used throughout the IC industry in VFB op amps, both precision and high speed. It can be recalled that a similar topology with a dual FET input stage was used in the early high speed, fast settling FET modular op amps (see "Op Amp History").
Another popular VFB op amp architecture is the folded cascode as shown in Figure 1-102 below. An industry-standard video amplifier family (the AD847) is based on this architecture. This circuit also takes advantage of the fast PNPs available on a CB process. The differential signal currents in the collectors of Q1 and Q2 are fed to the emitters of a PNP cascode transistor pair (hence the term folded cascode). The collectors of Q3 and Q4 are loaded with the current mirror, D1 and Q5, and voltage gain is developed at the Q4-Q5 node. This single-stage architecture uses the junction capacitance at the highimpedance node for compensation (CSTRAY). Some variations of the design bring this node to an external pin so that additional external capacitance can be added if desired.
AD847-family folded cascode simplified circuit
Figure 1-102: AD847-family folded cascode simplified circuit
With no emitter degeneration resistors in Q1 and Q2, and no additional external compensating capacitance, this circuit is only stable for high closed-loop gains. However, unity-gain compensated versions of this family are available which have the appropriate amount of emitter degeneration.
The availability of JFETs on a CB process allows not only low input bias current but also improvements in the slew rate tradeoff, which must be made between gm and IT found in bipolar input stages. Figure 1-103 (opposite) shows a simplified diagram of the AD845 16MHz op amp. JFETs have a much lower gm per mA of tail current than a bipolar transistor. This lower gm of the FET allows the input tail current (hence the slew rate) to be increased, without having to increase CP to maintain stability.
The unusual thing about this seemingly poor performance of the JFET is that it is exactly what is needed for a fast, high SR input stage. For a typical JFET, the value of gm is approximately Is/1V (Is is the source current), rather than Ic/26mV for a bipolar transistor,  i.e., the FET gm is about 40 times lower. This allows much higher tail currents (and higher slew rates) for a given gm when JFETs are used as the input stage.
AD845 BiFET 16MHz op amp simplified circuit
Figure 1-103: AD845 BiFET 16MHz op amp simplified circuit
A New VFB Op Amp Architecture for "Current-on-Demand" Performance, Lower Power, and Improved Slew Rate
Until recently, op amp designers had to make the above tradeoffs between the input gm stage quiescent current and the slew-rate and distortion performance. ADI has patented a circuit core which supplies current-on-demand, to charge and discharge the dominant pole capacitor, CP, while allowing the quiescent current to be small. The additional current is proportional to the fast slewing input signal and adds to the quiescent current.
Figure 1-104: "Quad-Core" VFB gm stage for current-on-demand
A simplified diagram of the basic core cell is shown in Figure 1-104 above. The quad-core (gm stage) consists of transistors Q1, Q2, Q3, and Q4 with their emitters connected together as shown. Consider a positive step voltage on the inverting input. This voltage produces a proportional current in Q1 that is mirrored into CP1 by Q5. The current through Q1 also flows through Q4 and CP2.
At the dynamic range limit, Q2 and Q3 are correspondingly turned off. Notice that the charging and discharging current for CP1 and CP2 is not limited by the quad core bias current. In practice, however, small current-limiting resistors are required forming an "H" resistor network as shown. Q7 and Q8 form the second gain stage (driven differentially from the collectors of Q5 and Q6), and the output is buffered by a unity-gain complementary emitter follower (X1).
The quad core configuration is patented (Reference 1: Roy Gosser, "Wide-Band Transconductance Generator," US Patent 5,150,074, filed May 3, 1991, issued September 22, 1992), as well as the circuits that establish the quiescent bias currents (not shown in Fig. 1-104). A number of new VFB op amps using this proprietary configuration have been released and have unsurpassed high frequency low distortion performance, bandwidth, and slew rate at the indicated quiescent current levels as shown in Figure 1-105 below.
High speed VFB op amps
Figure 1-105: High speed VFB op amps
The AD9631, AD8074, and AD8047 are optimized for a gain of +1, while the AD9632, AD8075, and AD8048 for a gain of +2.
The same quad-core architecture is used as the second stage of the AD8041 rail-to-rail output, zero-volt input single-supply op amp. The input stage is a differential PNP pair which allows the input common-mode signal to go about 200mV below the negative supply rail. The AD8042 and AD8044 are dual and quad versions of the AD8041.
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