The conventional three-phase six-switch VSC is shown in Figure 6.32. It consists of six switches *S _{1}-S_{6}* and six antiparallel diodes

*D*. The number indicates their order of being turned on. A fictitious neutral (

_{1}-D_{6}*o*) as a mid-point is also included although in most cases is not available. However, when the converter under consideration is used as an active filter in the case of a four-wire three-phase system, this point (

*o*) is used to connect the fourth-wire. This case will be discussed further in later parts.

The three converter legs are controlled with a phase-shift of 120^{o} between them. The basic way to control the three-phase six-switch VSC is to turn on each switch for half of the period (180^{0}) with a sequence 1, 2, 3, . . . as they are numbered and shown in Figure 6.32.

Fig. 6.32 Conventional three-phase six-switch VSC.

The operation of the converter can be explained with the assistance of Figure 6.33. Specifically, the control signals for each of the six switches are shown in Figure 6.33(a). Clearly, each switch remains on for 180^{0} and every 60^{0} a new switch is turned on and one of the previous group is turned off. At any given time therefore, one switch of each leg is on. Assuming that the fictitious mid-point (0) is available, three square-type waveforms for the voltages *v*_{AO}, *v*_{BO}, and *v*_{CO} can be drawn as shown in Figure 6.33(b). Each of the voltage waveforms has two peak values of *V*_{dc}/2, and -*V*_{dc}/2, and they are displaced by 120^{o} from each other.

From the three waveforms *v*_{AO}, *v*_{BO}, and *v*_{CO}, the line-to-line voltage waveforms can be drawn since

The three resultant line-to-line voltage waveforms are then shown in Figure 6.33(c). It is clear that each waveform takes three values (*V*_{dc}, 0, -*V*_{dc}) and there is a 120^{o} phase-shift between them. These waveforms have a 60^{o} interval when they are zero for each half of the period, a total of 120o per period. As explained earlier, each leg can handle current in both directions at any time, since either the turned on switch or the antiparallel diode of the other switch can be the conducting element depending upon the polarity of the output line current.

The potential of the load neutral point (*n*) shown in Figure 6.32 with respect to the mid-point of the DC bus (*0*) is drawn in Figure 6.33(d). It can be seen that such a waveform has frequency three times the output frequency and the two peak values are between *V*_{dc}/6 and -*V*_{dc}/6. Finally, the line-to-load neutral point (*n*) voltage waveform is illustrated in Figure 6.33(e). Such a voltage waveform has two positive values (*V*_{dc}/3 and 2*V*_{dc}/3) and two negative ones (-*V*_{dc}/3 and -2*V*_{dc}/3).

Fig. 6.33 Key waveforms of the three-phase six-step VSC circuit operation. (a) control signals for switches *S*_{1}, *S*_{2}, *S*_{3}, *S*_{4} ,*S*_{5} , S6; (b) voltage waveforms *v*_{AO}, *v*_{BO}, and *v*_{CO}; (c) output line-to-line voltage waveforms *v*_{AB}, *v*_{BC}, *v*_{CA} ; (d) voltage waveform between the load neutral point (*n*) and the DC bus mid-point (*0*); (e) voltage waveform between the line point A and the load neutral point *n*; (f) harmonic spectrum of the line-to-DC bus mid-point; and (g) harmonic spectrum of the line-to-line voltage *v*_{AB}.

The harmonics of the various waveforms can be calculated using Fourier series. The fundamental amplitude of the voltage waveforms *v*_{AO}, *v*_{BO}, and *v*_{CO} is

where *h* is the order of the harmonic.

For the line-to-line voltage waveforms *v*_{AB}, *v*_{BC}, and *v*CA then the fundamental amplitude is

and therefore the rms value of the fundamental component is then

Similarly, the amplitude of the harmonic voltages is

The rms value of the line-to-line voltage including all harmonics is

The normalized spectrum of the line-to-DC bus mid-point and the line-to-line voltage waveforms are plotted in Figures 6.33(f) and (g) respectively. It can be seen that the voltage waveforms *v*_{AO}, *v*_{BO}, and *v*_{CO} contain all odd harmonics. The load connection as shown in Figure 6.32 does not allow 3rd harmonic and all multiples to flow, and this is confirmed with the spectrum of the line-to-line voltage waveform *v*_{AB} where 3rd, 9th and 15th harmonics are eliminated as shown in Figure 6.33(g).

previous **Single-phase full-bridge VSC**

next **Single-phase half-bridge neutral-point-clamped (NPC) vSC**

In this section we will examine in detail the single-phase full-bridge VSC. Its power circuit is shown in Figure 6.26. It consists of two identical legs like the half-bridge single-phase converter (Figure 6.23) discussed in Section 6.3.1. Specifically, there are four switching elements (*S*_{1}, *S*_{2}, *S*_{3}, *S*_{4}), four antiparallel diodes (*D*_{1}, *D*_{2}, *D*_{3}, *D*_{4}) and a DC bus voltage source *V*_{dc}* *that can be a single capacitor. The other leg provides the return path for the current this time and the DC bus mid-point does not need to be available to connect the load. The output voltage *v _{0}* appears across the two points

*A*and

*B*as shown in Figure 6.26.

The control restriction discussed for the single-phase half-bridge topology (Figure 6.23) applies to this converter as well. Clearly the control signals for the switch pairs (*S*_{1}, *S*_{2}) and (*S*_{3}, *S*_{4}) must be complementary to avoid any bridge destruction due to shoot through of infinite current (at least theoretically).

There are two control methods for this topology. The first one treats the switches (*S*_{1}, *S*_{4}) and (*S*_{2}, *S*_{3}) as a pair. This means that they are turned on and off at the same time and for the same duration. For square-wave operation the switches *S*_{1} and *S*_{4} are on for half of the period. For the other half, the pair of *S*_{2}, *S*_{3} is turned on. Like the single-phase half-bridge VSC, the direction of the output current *i*_{0} determines the conduction state of each semiconductor.

When the two switches *S*_{1} and *S*_{4} are turned on, the voltage at the output is equal to the DC bus voltage *V*_{dc}. Similarly, when the switches *S*_{2 }and *S*_{3} are turned on the output voltage is equal to - *V*_{dc}. Such circuit operation is illustrated in Figure 6.27.

In the first case, when the direction of the output current *i*_{o} is positive as shown in Figure 6.26, the current flows through switches *S*_{1} and *S*_{4} and the power is transferred from the DC side to the AC one (*t*_{4} < *t* < *t*_{5}). When the current becomes negative, although the switches *S*_{1} and *S*_{4} are turned on, the diodes *D*_{1} and *D*_{4} conduct the current and return power back to the DC bus from the AC side (*t*_{3} < *t* < *t*_{4}). For the other half of the period, when the switches *S*_{2 }and *S*_{3} are turned on and the current is positive, the diodes *D*_{2} and *D*_{3} conduct (*t*_{1} < *t* < *t*_{2}). In this

Fig. 6.26 Single-phase full-bridge VSC.

Fig. 6.27 Key waveforms of the single-phase full-bridge VSC circuit operation. (a) output voltage *V*_{0} = *V*_{AB}; (b) output current *i*_{0}; (c) input DC bus current *i*_{d}; (d) harmonic spectrum of the output voltage *V*_{0} = *V*_{AB}; (e) harmonic spectrum of the output current *i*_{0}; and (f) harmonic spectrum of the input DC bus current *i*_{d}.

instance, power is transferred also back to the DC side from the AC side. Finally, when the current is negative, the switches *S*_{2} and *S*_{3 }carry the current and assist the converter to transfer power from the DC bus to the AC side (*t*_{2} < *t* < *t*_{3}). In summary, there are four distinct modes of operation for this converter when the control method shown in Figure 6.27 is employed (two inverter modes and two rectifier modes). Simply said, at all times two switches are turned on and the legs are controlled in a synchronized way.

The output voltage *v*_{0} = *v*_{AB} is shown in Figure 6.27(a). The output current *i*_{0} and the input DC current *i*_{d} are also plotted in Figures 6.27(b) and (c) respectively. Similarly, like the case of the half-bridge topology, the square-wave generated across the AC side includes all odd harmonics and being a single-phase system, the third harmonic is also present (Figure 6.27(d)). These harmonics when reflected back to the DC side source include all even harmonics (Figure 6.27(f).

Fig. 6.28 Quadrants of operation of the single-phase full-bridge VSC.

The fundamental component of the output voltage *v*_{0} waveform has an amplitude value of

(6.20)

And its various harmonics are given by

where *h *is the order of the harmonic.

The converter is capable of operating in all four quadrants of voltage and current as shown in Figure 6.28. The various modes and their relationship to the switching and/or conduction state of the semiconductors are also summarized in Table 6.4 for further clarity. The phase relationship between the AC output voltage and AC output current does not have to be fixed and the converter can provide real and reactive power at all leading and lagging power factors. However, the converter itself cannot control the output voltage if the DC bus voltage *V*_{dc} remains constant. There is a need to adjust the level of the DC bus voltage if one wants to control the rms value of the output voltage *v*_{0}.

There is however a way to control the rms value of the fundamental component of the output voltage as well as the harmonic content of the fixed waveform shown in Figure 6.27(a). In this method, the control signals of the two legs are not

**Table 6.4 Modes of operation of the single-phase full-bridge VSC**

synchronized in any way and the switches are not treated as pairs like previously. For the safe operation of the converter, the control signals between (S_{1} and S_{2}) and (S_{3} and S_{4}) must be complementary. In this case, there is a phase- shift between the two legs and this way a zero volts interval can appear across the output.

For instance, if switches S_{1} and S_{3} are turned on at the same time, the output voltage (*v*_{AB}) will be zero. The current in the case of other than unity power factor must keep flowing. There is no power exchange between the DC side and the AC one (free-wheeling mode). If the current is positive, the current flows through S_{1} and D_{3}. If the current is negative, it flows through D_{1} and S_{3}. Similarly, when the two bottom switches S_{2} and S_{4} are turned on at the same time, the output voltage (*v*_{AB}) is zero and the output current once again determines which element conducts and allows the output current to continue flowing. Specifically, if the current is positive, the diode D_{2} and the switch S_{4} are conducting. In the case that the current is negative, the switch S_{2} and diode D_{4} provide a path for the output current. These extra modes of operation for the single-phase full-bridge topology (Figure 6.26) are also included in Table 6.4 as the free-wheeling modes.

For a given phase-shift (a degrees) between the control signals of the two legs, the waveforms are shown in Figure 6.29. It is clear that the output voltage waveform is a three-level one, being able to have the values of *V*_{dc}, 0 and -*V*_{dc} as shown in Figure 6.29(a). The control signals are shown in Figures 6.29(b)-(d). It is also clear that between the top and bottom switches of each leg complementary control signals are used. It should be noted that for α = 0, the output voltage becomes similar to the previously presented control method (square-wave, Figure 6.27(a)).

The output voltage *v*_{o} (*v*_{AB}) is shown in Figure 6.30(a) along with the output current *i*_{o} and the DC bus current *i*_{d} in Figures 6.30(b) and (c) respectively. Therefore, by controlling the phase-shift between the two legs (α degrees), the rms value of the fundamental component can be controlled. The amplitude of all odd harmonics, as shown in Figure 6.30(d) for the output voltage, can also be controlled. The output current has only a fundamental component as shown in Figure 6.30(e), where the DC bus current has a DC component and all even harmonics as shown in Figure 6.30(f).

Fig. 6.29 Key waveforms of the single-phase full-bridge phase-shifted controlled VSC circuit operation. (a) output voltage *v*_{o} = *v*_{AB}; (b) control signal for switch S_{1} ; (c) control signal for switch S_{2}; (d) control signal for switch S_{3}; and (e) control signal for switch S_{4}.

Fig. 6.30 Key waveforms of the single-phase full-bridge phase-shifted controlled VSC circuit operation. (a) output voltage *v*_{o} = *v*_{AB}; (b) output current *i*_{o}; (c) DC bus current *i*_{d}; (d) harmonic spectrum of the output voltage *v*_{o} = *v*_{AB}; (e) harmonic spectrum of the output current *i*_{o}; and (f) harmonic spectrum of the input DC bus current id.

Fig. 6.31 Normalized amplitudes of fundamental and harmonics for the phase-shifted output voltage as a function of α (zero volts interval in degrees).

For a given zero interval α in degrees, as shown in Figures 6.29(a) and 6.30(a), the amplitude of the fundamental and harmonics are as follows

where *h* is the order of the harmonic.

When α = 0 the converter operates as a square-wave one (Figure 6.27). The normalized amplitude of the fundamental and the most significant harmonics, i.e. 3rd, 5th, 7th and 9th to the output of the square-wave converter as a function of α, are plotted in Figure 6.31.

previous **Single-phase half-bridge VSC**

next **Conventional three-phase six-step VSC**

_{1}and S

_{2}) with two antiparallel diodes (D

_{1}and D

_{1}) to accommodate the return of the current to the DC bus when required. This happens when the load power factor is other than unity. In order to generate a mid-point (0) to connect the return path of the load, two equal value capacitors (C

_{1}and C

_{2}) are connected in series across the DC input. The result is that the voltage

*V*

_{dc}

*is split into two equal sources across each capacitor with voltage of*

*V*

_{dc}/2. The assumption here is that the value of the capacitors is sufficiently large to ensure a stiff DC voltage source. This simply means that their voltage potential remains unchanged during the operation of the circuit. This also means that the potential of the mid-point (

*0*) is constant with respect to both positive and negative DC bus rails at all times (

*V*

_{dc}/2) and -

*V*

_{dc}/2 respectively).

*S*

_{1}and

*S*

_{2}are complementary to avoid destruction of the bridge. This would happen due to the throughput of high current coming from the low impedance DC voltage sources, if both switches were turned on simultaneously. When the switch

*S*

_{1}is turned on

*(t*

_{3}

*<*

*t*<

*t*

_{5}), the output voltage

*v*=

_{0}*v*

_{AO}is equal to the voltage

*V*

_{dc}/2 of the capacitor

*C*

_{1}. The mode of operation of the switching block (

*S*

_{1}and

*D*

_{1}) is then controlled by the polarity of the output current

*i*

_{0}. If the output current is positive, with respect to the direction shown in Figure 6.23, then the current is flowing through switch

*S*

_{1}(

*t*

_{4}<

*t*<

*t*

_{5}, Figure 6.24). If the output current is negative, the diode

*D*

_{1}is conducting, although switch

*S*

_{1}is turned on (

*t*

_{3}<

*t*<

*t*

_{4}). Similarly, if the switch

*S*

_{2}is turned on (

*t*

_{1}<

*t*<

*t*), the output voltage is equal to the voltage

_{3}*V*

_{dc}/2 of the capacitor

*C*

_{2}with the polarity appearing negative this time. The output current

*i*

_{0}once again determines the conduction state of the switch and diode. If the output current is positive, the diode

*D*

_{2}is conducting (

*t*

_{1}<

*t*<

*t*

_{2}). If the output current is negative, the current flows through switch

*S*

_{2}(

*t*

_{2}<

*t*<

*t*

_{3}). Such states of switches and diodes are clearly marked in the waveforms of Figure 6.24 for the various time intervals. The modes of operation of the half-bridge single-phase VSC are also summarized in Table 6.3.

*v*

_{0}

*=*

*v*

_{A0}generated by the converter operation as previously explained. Due to the square-wave generated by the converter, the output voltage waveform is rich in harmonics. Specifically, as shown in Figure 6.24(c) all odd harmonics are present in the spectrum of the output voltage. The fact that the converter cannot control the rms value of the output voltage waveform at fundamental frequency is also a limitation. A separate arrangement must be made to vary the DC bus voltage

*V*

_{dc}in order to vary and control the output voltage

*v*

_{0}.

**Fig. 6.24**Key waveforms of the single-phase half-bridge VSC circuit operation. (a) output voltage

*V*

_{0 }=

*V*

_{A0}; (b) output current

*i*

_{0}; and (c) harmonic spectrum of the output voltage

*V*

_{0 }=

*V*

_{A0}.

*v*

_{0}shown in Figure 6.24(a) can be expressed using Fourier series as follows

*h*is the order of the harmonic.

**Fig. 6.25**quadrants of operation of the single-phase half-bridge VSC.

*S*

_{1}and

*S*

_{2}perform this function. In the case that the power is negative, which means power is returned back to the DC bus from the AC side, the converter operates as a rectifier. The diodes

*D*

_{1}and

*D*

_{1}perform this function.

*S*

_{1}and the antiparallel diode

*D*

_{1}) and (

*S*

_{2}and

*D*

_{2}) can be used as a leg to build three-phase and other types of converters with parallel connected legs and other topologies. These types of converters will be described later.

**Voltage-source converters (VSCs) and derived controllers**

**Single-phase full-bridge VSC**

- Voltage-source converters or else voltage-source inverters (VSIs): the DC bus input is a voltage source (typically a capacitor) and its current through can be either positive or negative. This allows power flow between the DC and AC sides to be bidirectional through the reversal of the direction of the current.
- Current-source converters (CSCs) or else current-source inverters (CSIs): the DC bus input is a current source (typically an inductor in series with a voltage source, i.e. a capacitor) and its voltage across can be either positive or negative. This also allows the power flow between the DC and AC sides to be bidirectional through the reversal of the polarity of the voltage.

**Switching transients in the general case**

**Single-phase half-bridge VSC**

*v*=

*v̂*sin (ω

_{0}t + α). Time is measured from the first instant when a thyristor is gated, corresponding to the angle α on the voltage wave- form. By straightforward transform manipulation and inverse transformation we get the instantaneous current expressed as

_{n}is the natural frequency of the circuit

(6.13)

*n*is the per-unit natural frequency.

The current has a fundamental-frequency component

*i*

_{AC}which leads the supply voltage by π/2 radians. Its amplitude

*î*

_{AC}is given by

(6.15)

*B*(

_{c}n^{2}/*n*1). The term

^{2}-*n*(

^{2}/*n*1) is a magnification factor, which accounts for the partial series-tuning of the L-C circuit. If there is appreciable inductance,

^{2}-*n*can be as low as 2.5, or even lower, and the magnification factor can reach l .2 or higher. It is plotted in Figure 6.18.

_{n}. In practice, resistance causes these terms to decay. The next section considers the behavior of the oscillatory components under important practical conditions.

*n*/(

^{2}*n*

^{2}- 1).

**1.**

*For transient-free switching, the oscillatory components of current in equation (6.12) must be zero. This can happen only when the following two conditions are simultaneously satisfied:*

**Necessary condition for transient-free switching**.*v̂n*(

^{2}/*n*- 1) with the same polarity. The presence of inductance means that for transient-free switching the capacitor must be 'overcharged' beyond

^{2}*v̂*by the magnification factor

*n*(

^{2}/*n*- 1). With low values of

^{2}*n*, this factor can be appreciable (Figure 6.18).

*V*,

_{C0}*n,*and

*v̂*can all vary during the period of non- conduction before the thyristors are gated. The capacitor will be slowly discharging, reducing

*V*; while the supply system voltage and effective inductance may change in an unknown way, changing

_{C0}*n.*In general, therefore, it will be impossible to guarantee perfect transient-free reconnection.

*v̂n*(

^{2}/*n+2*- 1).

**2.**There are some circumstances in which equations (6.16) and (6.17) are far from being satisfied. One is when the capacitor is completely discharged, as for example when the compensator has been switched off for a while. Then

*Switching transients under non-ideal conditions.**V*

_{C0}= 0. There is then no point on the voltage wave when both conditions are simultaneously satisfied.

*V*

_{C0}can have any value, depending on the conditions under which conduction last ceased and the time since it did so. The question then arises, how does the amplitude of the oscillatory component depend on

*V*

_{C0}? How can the gating instants be chosen to minimize the oscillatory component? Two practical choices of gating are: (a) at the instant when

*v*=

*V*

_{C0}, giving sin α =

*V*

_{C0}/

*v̂*; and (b) when d

*v*/d

*t*= 0, giving cos α = 0. The first of these may never occur if the capacitor is overcharged beyond

*v̂*. The amplitude

*î*

_{osc}of the oscillatory component of current can be determined from equation (6.12) for the two alternative gating angles. In Figures 6.19 and 6.20 the resulting value of

*î*

_{osc}relative to

*î*

_{AC}is shown as a function of

*V*

_{C0}and

*n,*for each of the two gating angles.

*V*

_{C0}is exactly equal to

*v̂*, the oscillatory component of current is non-zero and has the same amplitude for both gating angles, whatever the value of the natural frequency

*n.*For any value of

*V*

_{c0}less than

*v̂*, gating with

*v*=

*V*

_{C0}always gives the smaller oscillatory component whatever the value of

*n.*

*v*=

*Vco.*

*v*/d

*t*= 0.

*n*= 2.3 and

*n*= 3.6.

**Switching a discharged capacitor**

*V*

_{C0}= 0. The two gating angles discussed were: (a) when

*v*=

*V*

_{C0}= 0; and (b) when d

*v/*d

*t*= 0 ( cos α = 0). In the former case only equation (6.17) is satisfied. From equation (6.12) it can be seen that in the second case (gating when dv/dt = 0) the oscillatory component of current is greater than in the first case (gating when

*v*=

*V*

_{C0}= 0). An example is shown in Figure 6.21 and Figure 6.22.

*V*=

*V*

_{C0}= 0; (b) gating when d

*v*/d

*t*= 0.

*î*

_{AC}= 1 p.u. and the natural frequency is given by

*n*=

*X*

_{C}((

*X*

_{S}+

*X*

_{T}) = 3.6 p.u. In case (a), the amplitude of the oscillatory component of current is exactly equal to

*î*

_{AC}. In case (b), the oscillatory component has the amplitude

*nî*

_{AC}and much higher current peaks are experienced. The capacitor experiences higher voltage peaks and the supply voltage distortion is greater.

**Switching transients and the concept of transient-free switching**

**Voltage-source converters (VSCs) and derived controllers**

**Ideal transient-free switching**

_{0}t + α), the thyristors can be gated into conduction only at a peak value of voltage, that is, when

*i*=

*C*dv/dt to have a discontinuous step change at

*t*= 0+. Such a step is impossible in practice because of inductance, which is considered in the next section. To permit analysis of Figure 6.16, the gating must occur at a voltage peak, and with this restriction the current is given by

_{0}C = B

_{C}is the fundamental-frequency susceptance of the capacitor, and X

_{C}= 1/B

_{C}its reactance, so that with α = ±π/2

*î*is the peak value of tha AC current,

_{AC}*î*

_{AC}=v̂B_{C}= v̂/X_{C }.*V*

_{C0}= ±

*v̂*, that is, it must hold the prior charge ±

*v̂/C.*This is because any prior DC voltage on the capacitor cannot be accounted for in the simple circuit of Figure 6.16. In practice this voltage would appear distributed across series inductance and resistance with a portion across the thyristor switch.

_{C0}= ±

*v̂*at t = 0, we have the ideal case of transient-free switching, as illustrated in Figure 6.15. This concept is the basis for switching control in the TSC. In principle, once each capacitor is charged to either the positive or the negative system peak voltage, it is possible to switch any or all of the capacitors on or off for any integral number of half-cycles without transients.

**The thyristor-switched capacitor (TSC)**

**Switching transients in the general case**

**Principles of operation**

*k*capacitors in parallel, each controlled by a switch as in Figure 6.13, the total susceptance can be equal to that of any combination of the

*k*individual susceptances taken 0, 1, 2 . . . . or

*k*at a time. The total susceptance thus varies in a stepwise manner. In principle the steps can be made as small and as numerous as desired, by having a sufficient number of individually switched capacitors. For a given number

*k*the maximum number of steps will be obtained when no two combinations are equal, which requires at least that all the individual susceptances be different. This degree of flexibility is not usually sought in power-system compensators because of the consequent complexity of the controls, and because it is generally more economic to make most of the susceptances equal. One compromise is the so-called binary system in which there are

*(k*- 1) equal susceptances B and one susceptance B/2. The half-susceptance increases the number of combinations from

*k*to

*2k.*

**The thyristor-controlled transformer (TCT)**

**Switching transients and the concept of transient-free switching**

**The TCR with shunt capacitors**

_{C max}and I

_{L max}the control characteristic is again represented by equation (6.6). However, if the voltage regulator gain is unchanged, the slope reactance X

_{S}will be slightly increased when the capacitors are added.

**Thyristor-controlled equipment**

next

**The thyristor-switched capacitor (TSC)**

**Thyristor-controlled reactor (TCR)**

**Principles of operation of the TCR**

*i*is given by

*V*is the rms voltage; X

_{L}= ωL is the fundamental-frequency reactance of the reactor (in Ohms); ω = 2π

*f*; and α is the gating delay angle. The time origin is chosen to coincide with a positive-going zero-crossing of the voltage. The fundamental component is found by Fourier analysis and is given by

_{L}(σ) is an adjustable fundamental-frequency susceptance controlled by the conduction angle according to the law

_{L}is 1/X

_{L}, obtained with σ = π or 180, that is, full conduction in the thyristor controller. The minimum value is zero, obtained with σ = 0 (α=180°). This control principle is called phase control.

**Fundamental voltage/current characteristic**

_{L}. In others, the control algorithm processes various measured parameters of the compensated system (e.g. the voltage) and generates the gating pulses directly with- out using an explicit signal for B

_{L}. In either case the result is a voltage/current characteristic of the form shown in Figure 6.4. Steady-state operation is shown at the point of intersection with the system load line. In the example, the conduction angle is shown as 130°, giving a voltage slightly above 1.0 p.u., but this is only one of an infinite number of possible combinations, depending on the system load line, the control settings, and the compensator rating. The control characteristic in Figure 6.4 can be described by the equation

*I*is normally the rated current of the reactors shown here as 1 put.

_{max}**Harmonics**

*nth*harmonic component is given by

^{a}

Harmonic order | Percentage |

1 | 100.00 |

3 | (13.78)^{b} |

5 | 5.05 |

7 | 2.59 |

9 | (1.57) |

11 | 1.05 |

13 | 0.75 |

15 | (0.57) |

17 | 0.44 |

19 | 0.35 |

21 | (0.29) |

23 | 0.24 |

25 | 0.20 |

27 | (0.17) |

29 | 0.15 |

31 | 0.13 |

33 | (0.12) |

35 | 0.10 |

37 | 0.09 |

^{a}Values are expressed as a percentage of the amplitude of the fundamental component at full conduction.

^{b}The values apply to both phase and line currents, except that triples harmonics do not appear in the line currents. Balanced conditions are assumed.

With both 6-pulse and 12-pulse TCR compensators, the need for filters and their frequency responses must be evaluated with due regard to the possibility of unbalanced operation. The influence of other capacitor balks and sources of harmonic currents in the electrical neighbourhood of the compensator must also be taken into account. For this purpose, several software packages are available and some examples with a specific one will be provided later.

The 12-pulse connection has the further advantage that if one half is faulted the other may be able to continue to operate normally. The control system must take into account the 30° phase shift between the two TCRs, and must be designed to ensure accurate harmonic cancellation. A variant of the 12-pulse TCR uses two separate transformers instead of one with two secondaries.

**Power electronic equipment**

**The thyristor-controlled transformer (TCT)**