2.1 INVERTERS
The main objective of static power converters is to produce an ac output waveform from a dc power supply. These are the types of waveforms required in adjustable speed drives (ASDs), uninterruptible power supplies (UPS), static var compensators, active filters, flexible ac transmission systems (FACTS), and voltage compensators, which are only a few applications. For sinusoidal ac outputs, the magnitude, frequency, and phase should be controllable. According to the type of ac output waveform, these topologies can be considered as voltage source inverters (VSIs), where the independently controlled ac output is a voltage waveform. These structures are the most widely used because they naturally behave as voltage sources as required by many industrial applications, such as adjustable speed drives (ASDs), which are the most popular application of inverters.
2.1.1 SINGLE PHASE INVERTER
2.1.1.1 SINGLE-PHASE HALF-BRIDGE VSI
A single-phase half-bridge VSI is shown in Figure 6.2. The carrier-based PWM technique is applied in this single-phase half-bridge VSI. Two large capacitors are required to provide a neutral point N, therefore, each capacitor keep the half of the input DC voltage. Two switches S+ and S− are switched by the PWM signal.
Figure 2.1 shows the ideal waveforms associated with the half-bridge VSI. We can find out the output of the phase delayed between the output current and voltage.
Figure2.1: Single-phase half-bridge VSI.
Figure 2.2: Ideal waveforms associated with the single-phase half-bridge VSI (ma =0.8, mf =9). (a) Carrier and modulating signals, (b) switch S+ state.
Figure 2.2: Ideal waveforms associated with the single-phase half-bridge VSI (ma =0.8, mf =9). (c) switch S− state, (d) AC output voltage and (e) AC output current.
2.1.1.2 SINGLE-PHASE FULL-BRIDGE VSI
A single-phase full-bridge VSI is shown in Figure 2.3. The carrier-based PWM technique is applied in this single-phase full-bridge VSI. Two large capacitors may be used to provide a neutral point N, therefore, each capacitor keep the half of the input DC voltage. Four switches S1+ and S1− plus S2+ and S2− are applied and switched by the PWM signal. Figure 2.4 shows the ideal waveforms associated with the full-bridge VSI. We can find out the output of the phase delayed between the output current and voltage. [8]
Figure 2.3: Single-phase full-bridge VSI.
Figure 2.4: Ideal waveforms associated with the full-bridge VSI (ma =0.8, mf =8). (a) Carrier and modulating signals, (b) switch S1+ and S1− state, (c) switch S2+ and S2− state, (d) AC output voltage and (e) AC output current.
2.1.2 THREE PHASE INVERTER2.1.2.1 THREE PHASE VOLTAGE SOURCE INVERTER WITH SQUARE WAVE OUTPUT
In this section a 3-phase bridge type VSI with square wave pole voltages has been considered. The output from this inverter is to be fed to a 3-phase balanced load. Fig.2.5 shows the power circuit of the three-phase inverter. This circuit may be identified as three single-phase half-bridge inverter circuits put across the same dc bus. The individual pole voltages of the 3-phase bridge circuit are identical to the square pole voltages output by single-phase half bridge or full bridge circuits. The three pole voltages of the 3-phase square wave inverter are shifted in time by one third of the output time period. These pole voltages along with some other relevant waveforms have been plotted in Fig. 2.6. The horizontal axis of the waveforms in Fig. 2.6 has been represented in terms of ‘ωt’, where ‘ω’ is the angular frequency (in radians per second) of the fundamental component of square pole voltage and ‘t’ stands for time in second. In Fig. 2.6 the phase sequence of the pole voltages is taken as VAO, VBO and VCO. The numbering of the switches in Fig. 2.5 has some special significance vis-à-vis the output phase sequence.
Figure 2.5: A 3-phase Voltage Source Inverter (VSI) feeding a balanced load
Figure 2.6: Some relevant voltage waveforms output by a 3-phase square wave VSI
To appreciate the particular manner in which the switches have been numbered, the conduction-pattern of the switches marked in Fig. 2.6 may be noted. It may be seen that with the chosen numbering the switches turn on in the sequence:- Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw1, Sw2, ….and so on. Identifying the switching cycle time as 360 degrees (2π radians), it can be seen that each switch conducts for 1800 and the turning on of the adjacent switch is staggered by 60 degrees. The upper and lower switches of each pole (leg) of the inverter conduct in a complementary manner. To reverse the output phase sequence, the switching sequence may simply be reversed.
Considering the symmetry in the switch conduction pattern, it may be found that at any time three switches conduct. It could be two from the upper group of switches, which are connected to positive dc bus, and one from lower group or vice-versa (i.e., one from upper group and two from lower group). According to the conduction pattern indicated in Fig. 2.6 there are six combinations of conducting switches during an output cycle:- (Sw5, Sw6, Sw1), (Sw6, Sw1, Sw2), (Sw1, Sw2, Sw3), (Sw2, Sw3, Sw4), (Sw3, Sw4, Sw5), (Sw4, Sw5, Sw6). Each of these combinations of switches conducts for 600 in the sequence mentioned above to produce output phase sequence of A, B, C. As will be shown later the fundamental component of the three output line-voltages will be balanced. The load side phase voltage waveforms turn out to be somewhat different from the pole voltage waveforms. [9]
2.1.2.2 THREE-PHASE FULL-BRIDGE VSI
A three-phase full-bridge VSI is shown in Figure 2.7. The carrier-based PWM technique is applied in this single-phase full-bridge VSI. Two large capacitors may be used to provide a neutral point N, therefore, each capacitor keep the half of the input DC voltage. Six switches S1–S6 are applied and switched by the PWM signal. Figure 6.7 shows the ideal waveforms associated with the full-bridge VSI. We can find out the output of the phase delayed between the output current and voltage. [10]
Figure 2.7: Three-phase full-bridge VSI.
Figure 2.8: Ideal waveforms associated with the three-phase full-bridge VSI (ma =0.8, mf =9). (a) Carrier and modulating signals, (b) switch S1+state, (c) switch S3 state, (d) AC output voltage and (e) AC output current.
2.2 RECTIFIERSAccording to controllability we have two types of rectifiers called controlled rectifiers and uncontrolled rectifiers. As the uncontrolled rectifiers indicate no need of controlling and hence no need for gate pulses, it is out of our interest. We will only focus on controlled rectifiers.
2.2.1 SINGLE-PHASE RECTIFIERS
2.2.1.1 SINGLE-PHASE HALF-WAVE CONTROLLED AC/DC RECTIFIER
The single-phase half-wave controlled AC/DC rectifier is shown in Figure 2.9. The load is an R–L circuit with a freewheeling diode. The SCR is conducted in the period from α to π, i.e. the conduction angle is π – α. The open-loop control block diagram is shown in Figure 2.10. The sampling interval is T =1/f, where f is the AC power supply source frequency. If f =50 Hz, then T =20 ms. This control can be implemented by a digital computer, which offers a firing pulse a cycle in 20 ms. The actuator is usually an R–L load. The final output parameter is the current IO shown in Figure 2.10.
Figure 2.9 Open-loop control block diagram.
Figure 2.10 Open-loop control block diagram.
The closed-loop control block diagram is shown in Figure 2.11. The sampling interval is T =1/f .A current controller is always requested in a closed-loop control system. It can be a proportional-plus-integral (PI) controller in digital form. This control can be implemented by a digital computer, which offers a firing pulse a cycle in 20 ms. The actuator is usually an R–L load. The final output parameter is the current IO shown in Figure 2.11.
Figure 2.11 Closed-loop control block diagram.
2.2.1.2 SINGLE-PHASE FULL-WAVEAC/DC RECTIFIER
The single-phase full-wave controlled AC/DC rectifier is shown in Figures 2.12(a) and (b). The load is an R–L circuit with continuous load current. Each SCR is conducted in the period of conduction angle π, from α to (π+α). The open-loop control block diagram is still shown in Figure 5.10. The sampling interval is T =1/2f , where f is the AC power supply source frequency. If f =50 Hz, then T =10 ms. This control can be implemented by a digital computer, which offers a firing pulse to each SCR a cycle in 20 ms. The actuator is usually an R–L load. The final output parameter is the current IO shown in Figure 2.10. The closed-loop control block diagram is shown in Figure 2.11. The sampling interval is T =1/2f , where f is the AC power supply source frequency. If f =50 Hz, then T =10 ms. This control can be implemented by a digital computer, which offers a firing pulse to each SCR a cycle in 20 ms. The actuator is usually an R–L load. The final output parameter is the current IO shown in Figure 2.11.
Figure 2.12 Single-phase full-wave controlled AC/DC rectifier with L–R load. (a) Center-tap(midpoint) circuit and (b) bridge (Graetz) circuit.
2.2.2 THREE-PHASE RECTIFIERS2.2.2.1 THREE-PHASE HALF-WAVE CONTROLLED AC/DC RECTIFIER
The three-phase half-wave controlled AC/DC rectifier is shown in Figures 2.13(a)–(d). The load is an R–L circuit with continuous load current. Each SCR is conducted in the period of conduction angle, 2π/3, from α to (2π/3+α). The open-loop control block diagram is still shown in Figure 2.10. The sampling interval is T =1/3f, where f is the AC power supply source frequency. If f =50 Hz, then T =6.67 ms. This control can be implemented by a digital computer, which offers a firing pulse to each SCR a cycle in 20 ms. The actuator is usually an R–L load. The final output parameter is the current IO shown in Figure 2.10. The closed-loop control block diagram is shown in Figure 2.11. The sampling interval is T =1/3f , where f is the AC power supply source frequency. If f =50 Hz, then T =6.67 ms. This control can be implemented by a digital computer, which offers a firing pulse to each SCR a cycle in 20 ms. The actuator is usually an R–L load. The final output parameter is the current IO shown in Figure 2.11.
Figure 2.13: Thee-phase half-wave controlled AC/DC rectifier. (a)Y/Y circuit, (b) ∆/Y circuit, (c) Y/Y bending circuit and (d) ∆/Y bending circuit.
2.2.2.2 THREE-PHASE FULL-WAVE CONTROLLED AC/DC RECTIFIER
The three-phase full-wave controlled AC/DC rectifier is shown in Figures 2.14(a)–(d). The load is an R–L circuit with continuous load current. Each SCR is conducted in the period of conduction angle 2π/3, from α to (2π/3+α). The open-loop control block diagram is still shown in Figure 5.10. The sampling interval is T =1/3f , where f is the AC power supply source frequency. If f =50 Hz, then T =6.67 ms. This control can be implemented by a digital computer, which offers a firing pulse to each SCR a cycle in 20 ms. The actuator is usually an R–L load. The final output parameter is the current IO shown in Figure 2.10. The closed-loop control block diagram is shown in Figure 2.11. The sampling interval is T =1/3f , where f is the AC power supply source frequency. If f =50 Hz, then T =6.67 ms. This control can be implemented by a digital computer, which offers a firing pulse to each SCR a cycle in 20 ms. The actuator is usually an R–L load. The final output parameter is the current IO shown in Figure 2.11.[10]
Figure 2.14: Three-phase full-wave controlled AC/DC rectifier. (a)Y/Y circuit, (b) ∆/Y circuit, (c) Y/∆ circuit and (d) ∆/∆ circuit.
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