Basic Structure of IGBT

The basic schematic of a typical N-channel IGBT based upon the DMOS process is shown in Figure 1. This is one of several structures possible for this device. It is evident that the silicon cross-section of an IGBT is almost identical to that of a vertical Power MOSFET except for the P+ injecting layer. It shares similar MOS gate structure and P wells with N+ source regions. The N+ layer at the top is the source or emitter and the P+ layer at the bottom is the drain or collector. It is also feasible to make P-channel IGBTs and for which the doping profile in each layer will be reversed. IGBT has a parasitic thyristor comprising the four-layer NPNP structure. Turn-on of this thyristor is undesirable. Some IGBTs, manufactured without the N+ buffer layer, are called non punch through (NPT) IGBTs whereas those with this layer are called punch-through (PT) IGBTs. The presence of this buffer layer can significantly improve the performance of the device if the doping level and thickness of this layer are chosen appropriately. Despite physical similarities, the operation of an IGBT is closer to that of a power BJT than a power MOSFET. It is due to the P+ drain layer (injecting layer) which is responsible for the minority carrier injection into the N–drift region and the resulting conductivity modulation. Based on the structure, a simple equivalent circuit model of an IGBT can be drawn as shown in Figure 2.

Figure 1: Schematic view of a generic N-channel IGBT

It contains MOSFET, JFET, NPN and PNP transistors. The collector of the PNP is connected to the base of the NPN and the collector of the NPN is connected to the base of the PNP through the JFET. The NPN and PNP transistors represent the parasitic thyristor which constitutes a regenerative feedback loop. The resistor RB represents the shorting of the base-emitter of the NPN transistor to ensure that the thyristor does not latch up, which will lead to the IGBT latchup. The JFET represents the constriction of current between any two neighboring IGBT cells. It supports most of the voltage and allows the MOSFET to be a low voltage type and consequently have a low RDS(on) value. A circuit symbol for the IGBT is shown in Figure 3. It has three terminals called Collector (C), Gate (G) and Emitter (E).

Figure 2: Equivalent circuit model of an IGBT

Figure 3: IGBT Circuit Symbol

Operation:

Forward-Blocking and Conduction Modes:

When a positive voltage is applied across the collector-to-emitter terminal with gate shorted to emitter shown in Figure 1, the device enters into forward blocking mode with junctions J1 and J3 are forward-biased and junction J2 is reverse-biased. A depletion layer extends on both-sides of junction J2 partly into P-base and N-drift region. An IGBT in the forward-blocking state can be transferred to the forward conducting state by removing the gate-emitter shorting and applying a positive voltage of sufficient level to invert the Si below gate in the P base region. This forms a conducting channel which connects the N+ emitter to the N--drift region. Through this channel, electrons are transported from the N+ emitter to the N--drift. This flow of electrons into the N—drift lowers the potential of the N--drift region whereby the P+ collector/ N--drift becomes forward-biased. Under this forward-biased condition, a high density of minority carrier holes is injected into the N--drift from the P+ collector. When the injected carrier concentration is very much larger the background concentration, a condition defined as a plasma of holes builds up in the N--drift region. This plasma of holes attracts electrons from the emitter contact to maintain local charge neutrality. In this manner, approximately equal excess concentrations of holes and electrons are gathered in the N - drift region. This excess electron and hole concentrations drastically enhance the conductivity of N--drift region. This mechanism in rise in conductivity is referred to as the conductivity modulation of the N--drift region.

Reverse-Blocking Mode:

When a negative voltage is applied across the collector-to-emitter terminal shown in Figure 1, the junction J1 becomes reverse-biased and its depletion layer extends into the N--drift region. The break down voltage during the reverse-blocking is determined by an open-base BJT formed by the P+ collector/ N--drift/P-base regions. The device is prone to punch-through if the N--drift region is very lightly-doped. The desired reverse voltage capability can be obtained by optimizing the resistivity and thickness of the N—drift region.

The width of the N--drift region that determines the reverse voltage capability and the forward voltage drop which increases with increasing width can be determined by

Where,
LP = Minority carrier diffusion length
Vm = Maximum blocking voltage
?₀ = Permittivity of free space
?_s = Dielectric constant of Si
q = Electronic charge
ND = Doping concentration of N-drift region
Latch-up:

During on-state, paths for current flow in an IGBT are shown in Figure 10. The holes are injected into the N--drift region from the P+ collector form two paths. Part of the holes disappear by recombination with electrons came from MOSFET channel. Other part of holes are attracted to the vicinity of the inversion layer by the negative charge of electrons, travel laterally through the P-body layer and develops a voltage drop in the ohmic resistance of the body. This voltage tends to forward bias the N+P junction and if it is large enough, substantial injection of electrons from the emitter into the body region will occur and the parasiric NPN transistor will be turned-on. If this happens, both NPN and PNP parasitic transistors will be turned-on and hence the thyristor composed of these two transistors will latch on and the latchup condition of IGBT will have occurred. Once in latchup, the gate has no control on the collector current and the only way to turn-off the IGBT is by forced commutation of the current, exactly the same as for a conventional thyristor. If latchup is not terminated quickly, the IGBT will be destroyed by the excessive power dissipation. IGBT has a maximum allowable peak drain current (ICM) that can flow without latchup. Device manufacturers specify this current level in the datasheet. Beyond this current level, a large enough lateral voltage drop will activate thyristor and the latchup of IGBT.

Safe Operating Area (SOA)

The safe operating area (SOA) is defined as the current-voltage boundary within which a power switching device can be operated without destructive failure. For IGBT, the area is defined by the maximum collector-emitter voltage VCE and collector current IC within which the IGBT operation must be confined to protect it from damage. The IGBT has the following types of SOA operations: forward-biased safe operating area (FBSOA), reverse-biased safe operating area (RBSOA) and short-circuit safe operating area (SCSOA).

Three Phase Topology

MODE	Sw1	Sw2	Sw3	Sw4	Sw5	Sw6	VAO	VBO	VCO
1	ON	OFF	OFF	OFF	ON	ON	+0.5 Edc	-0.5 Edc	+0.5 Edc
2	ON	ON	OFF	OFF	OFF	ON	+0.5 Edc	-0.5 Edc	-0.5 Edc
3	ON	ON	ON	OFF	OFF	OFF	+0.5 Edc	+0.5 Edc	-0.5 Edc
4	OFF	ON	ON	ON	OFF	OFF	-0.5 Edc	+0.5 Edc	-0.5 Edc
5	OFF	OFF	ON	ON	ON	OFF	-0.5 Edc	+0.5 Edc	+0.5 Edc
6	OFF	OFF	OFF	ON	ON	ON	-0.5 Edc	-0.5 Edc	+0.5 Edc
7	ON	OFF	OFF	OFF	ON	ON	+0.5 Edc	-0.5 Edc	+0.5 Edc
8	ON	ON	OFF	OFF	OFF	ON	+0.5 Edc	-0.5 Edc	-0.5 Edc
9	ON	ON	ON	OFF	OFF	OFF	+0.5 Edc	+0.5 Edc	-0.5 Edc
10	OFF	ON	ON	ON	OFF	OFF	-0.5 Edc	+0.5 Edc	-0.5 Edc
11	OFF	OFF	ON	ON	ON	OFF	-0.5 Edc	+0.5 Edc	+0.5 Edc
12	OFF	OFF	OFF	ON	ON	ON	-0.5 Edc	-0.5 Edc	+0.5 Edc

Relationships between pole voltages (V_AO, V_BO, V_CO) and line voltages (V_AB, V_BC, V_CA)
V_AB = V_AO – V_BO
V_BC = V_BO – V_CO
V_CA = V_CO – V_AO
Relationships between pole voltages (V_AO, V_BO, V_CO) and phase voltages (V_AN, V_BN, V_CN)
For a balance three phase system,
V_AN + V_BN + V_CN = 0            (1)
and,
V_AN = V_AO – V_NO                (2.1)
V_BN = V_BO – V_NO                (2.2)
V_CN = V_CO – V_NO                (2.3)
(2.1), (2.2), and (2.3) into (1),
V_AO + V_BO + V_CO – 3V_NO = 0
Therefore V_NO = 1/3(V_AO + V_BO + V_CO)
(3) into (2.1),
V_AN = V_AO – 1/3(V_AO + V_BO + V_CO) = 2/3 V_AO - 1/3 (V_BO + V_CO)
(3) into (2.2),
V_BN = 2/3 V_BO – 1/3 (V_AO + V_CO)
(3) into (2.3),
V_CN = 2/3 V_CO – 1/3 (V_AO + V_BO)