Single-Phase Half-Bridge VSI

For the half-bridge inverter circuit, the centre-tap of the DC supply is used as one of the load terminals. The centre-tap is created by the two series-connected equal-valued capacitors across the DC supply. The dc rail voltages are thus at +V_s/2 and −V_s/2 with respect to some fictitious ground potential.

The two switches, Q1 and Q2, are switched alternately, in a complementary fashion, at the desired output frequency, ƒ_o.

Power electronic converter: Single-Phase Half-Bridge VSI

Single-Phase Half-Bridge Inverter

When Q1 is ON, Q2 is OFF and the voltage at the terminal a of the load is +V_s/2 with irrespective of the direction of current through the load. Similarly, when Q2 is ON, the Q1 is OFF and the potential at point a is –V_s /2.
The load voltage is a square-wave of amplitude V_s /2. For a resistive load the current waveform follows the voltage waveform (as shown). For an inductive load the current waveform lags the voltage waveform by an angle which is, approximately, the load power factor angle.

RMS Output voltage and fundamental component of output voltage are given by:
${V_{0(rms)}} = \sqrt {\frac{2}{\pi } \smallint \limits_0^\pi {{\left( {\frac{{{V_S}}}{2}} \right)}^2}d\theta } = \frac{{{v_S}}}{2}$
${V_{0(rms)}} = \frac{{2{V_S}}}{{\sqrt 2 \pi }} = 0.45{V_S}$
The output voltage can be expressed in Fourier series as
${v_o}(t) = \sum\limits_{n - 1,3,5,..}^\infty {\frac{{2{V_S}}}{{n\pi }}} \sin n\omega t$
$= 0{\rm{ }}for{\rm{ }}n = 2,4,.....$

Function of antiparallel diodes, D1 and D2

Load current may not reverse at the same instants as does the load voltage. Current may lead or lag the output voltage due to the presence of capacitance and/or inductance in the load circuit. Diodes D₁ and D₂ in anti-parallel with each transistors permit load current to flow if necessary.

In the leading current case, the output current reverses its direction at t_X. Output voltage reverses its direction at T/2. Therefore, from t_X to T/2 the output current will flow through D₁.

In the lagging current case, the output current reverses its direction at t_Y. Output voltage reverses its direction at T/2. Therefore, from T/2 to t_Y the output current will flow through D₂.